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tc62d749afg/afnag/bfnag 2011-02-10 1 toshiba cdmos integrated circuit silicon monolithic tc62d749afg, TC62D749AFNAG, tc62d749bfnag 16-output constant current led driver (output switching high-speed version) tc62d749 series are an led driver with a sink type constant current output. it is the best for lighting the led module and the led display. this ic consists of a constant current output circuit of 16 outputs, a shift register of 16 bits, a latch of 16 bits, and 16 and gates. the output current of 16 output s can be set by one external resistance. moreover, high-speed data transfer is possible by adoption of a cmos process. this ic can operate with the po wer supply voltage of a 3.3 v system and a 5 v system. features ? power supply voltages : v dd = 3.3 v to 5.0 v ? 16-output built-in ? output current setting range : i out = 1.5 to 90 ma ? current accuracy (@ r ext = 1.2 k , v out = 1.0 v, v dd = 3.3 v, 5.0 v) : s rank between outputs 1.5 % (max) : s rank between devices: 1.5 % (max) : n rank between outputs 2.5 % (max) : n rank between devices: 2.5 % (max) ? output voltage : v out = 17 v (max) ? output switching characteristic : t woe = 25 ns (min), t or = 10ns (typ.), t of = 10ns (typ.) there is tc62d748 as an output switching st andard-speed version of this product. ? input signal voltage level : 3.3 v and 5.0 v cmos interfaces (schmitt trigger input) ? serial data transfer rate : 25 mhz (max) @cascade connection ? operation temperature range : t opr = ? 40 to 85 c ? power-on-reset function built-in : when the powe r supply is turned on, internal data is reset. ? package : afg type ssop24-p-300-1.00b : afnag type ssop24-p-150-0.64 : bfnag type ssop24-p-150-0.64 please ask toshiba sales dept or agent for details for products? name. when the led driver of high-speed ou tput switching is used, back emf may occur at the time of output off, and output terminal voltage may rise. please be careful. it is necessary to reduce inductance to prevent the back emf. it is possible to reduce inductance of a substrate by making the power supply for led wiring shorter and wider designing the layout pattern. tc62d749afg ssop24-p-300-1.00b TC62D749AFNAG/bfnag ssop24-p-150-0.64 weight ssop24-p-300-1.00b : 0.29 g (typ.) ssop24-p-150-0.64: 0.14 g (typ.)
tc62d749afg/afnag/bfnag 2011-02-10 2 block diagram out0 out1 constant current outputs out0 out1 out15 out15 16-bit d-latch g q0 q1 q15 d0 d1 d15 r 16-bit shift register d15 q0 q1 q15 r d0 slat oe sin sck por vdd gnd rext sout b.g vdd
tc62d749afg/afnag/bfnag 2011-02-10 3 pin assignment (top view) short circuiting an output pin to a power supply pin (power-supply voltage v dd and led anode power supply), or short-circuiting the r ext pin to the gnd pin will likely exceed the rati ng, which in turn may result in smoldering and/or permanent damage. please keep this in mind when determining the wiring layout for the power supply and gnd pins. pin functions pin no afg, afnag bfnag pin name i/o function 1 7 gnd ? the ground pin. 2 8 sin i the serial data input pin. 3 9 sck i the serial data transfer clock input pin. 4 10 slat i the latch signal input pin. data is saved at l level. 5 11 out0 o a sink type constant current output pin. 6 12 out1 o a sink type constant current output pin. 7 13 out2 o a sink type constant current output pin. 8 14 out3 o a sink type constant current output pin. 9 15 out4 o a sink type constant current output pin. 10 16 out5 o a sink type constant current output pin. 11 17 out6 o a sink type constant current output pin. 12 18 out7 o a sink type constant current output pin. 13 19 out8 o a sink type constant current output pin. 14 20 out9 o a sink type constant current output pin. 15 21 out10 o a sink type constant current output pin. 16 22 out11 o a sink type constant current output pin. 17 23 out12 o a sink type constant current output pin. 18 24 out13 o a sink type constant current output pin. 19 1 out14 o a sink type constant current output pin. 20 2 out15 o a sink type constant current output pin. 21 3 oe i the constant current output enable signal input pin. during the ?h? level, the output will be forced off. 22 4 sout o the serial data output pin. 23 5 rext ? the constant current value setting resistor connection pin. 24 6 vdd ? the power supply input pin. tc62d749afg/afnag tc62d749bfnag sout vdd rext gnd sin sck slat out0 out1 out2 out3 out4 out5 out6 out7 vdd rext sout oe out15 out14 out13 out12 out11 out10 out8 oe gnd sin slat out0 out1 sck out2 out3 out4 out5 out6 out7 out8 out9 out10 out11 out12 out13 out9 out14 out15
tc62d749afg/afnag/bfnag 2011-02-10 4 i/o equivalent circuits 1. sck, sin 2. oe 3. slat 4. sout 5. out0 to out15 vdd sout gnd vdd (sck) (sin) vdd oe vdd slat gnd gnd gnd 0 out to 15out gnd
tc62d749afg/afnag/bfnag 2011-02-10 5 truth table sck slat oe sin out0 ? out7 ? out15 *1 sout h l dn dn ? dn ? 7 ? dn ? 15 dn ? 15 l l dn + 1 no change dn ? 14 h l dn + 2 dn + 2 ? dn ? 5 ? dn ? 13 dn ? 13 ? *2 l dn + 3 dn + 2 ? dn ? 5 ? dn ? 13 dn ? 13 ? *2 h dn + 3 off dn ? 13 note1: when out0 to out15 output pins are set to "h" the respecti ve output will be on and when set to "l" the respective output will be off. note2: ?-? is irrelevant to the truth table. timing diagram ? the latch circuit is a leveled-latch circuit. please exer cise precaution as it is not triggered-latch circuit. ? keep the slat pin is set to ?l? to enable the latch circuit to hold data. in addition, when the slat pin is set to ?h? the latch circuit does not hold data. the data will instead pass onto output. when the oe pin is set to ?l? the out0 to out15 output pins will go on and off in response to the data. in addition, when the oe pin is set to ?h? all the output pins will be forced off regardless of the data. ? this product can use 3.3v and 5.0v power supply, but power supply and input (sck/sin/ slat / oe ) must use same voltage. sin slat sck out0 out1 sout oe out15 h l n = 0 1 2 3 4 5 6 8 h l h l h l on off on off on off on off h l 7911 10 12 13 1514 2out
tc62d749afg/afnag/bfnag 2011-02-10 6 absolute maximum rating s (t a = 25c) characteristics symbol rating *1 unit power supply voltage v dd ? 0.3 to 6.0 v output current i out 95 ma logic input voltage v in ? 0.3 to v dd + 0.3 *2 v output voltage v out ? 0.3 to 17 v operating temperature t opr ? 40 to 85 c storage temperature t stg ? 55 to 150 c thermal resistance rth(j-a) 94 (afg) *3, 80.07(afnag/bfnag) when mounted pcb c/w power dissipation p d *4 1.32 (afg) *3, 1.56(afnag/bfnag) when mounted pcb w note1: voltage is ground referenced. note2: do not exceed 6.0v. note3: pcb condition 76.2 x 114.3 x 1.6 mm, cu 30% (semi conforming) note4: the power dissipation decreases t he reciprocal of the saturated thermal resistance (1/ rth(j-a)) for each degree (1c) that the ambient temperature is exceeded (ta = 25c). operating conditions dc items (unless otherwise specified, v dd = 3.0 to 5.5 v, t a = ? 40c to 85c) characteristics symbol test conditions min typ. max unit power supply voltage v dd ? 3.0 ? 5.5 v high level logic input voltage v ih sin,sck, slat , oe 0.7 v dd ? v dd v low level logic input voltage v il sin,sck, slat , oe gnd ? 0.3 v dd v high level sout output current i oh ? ? ? ? 1 ma low level sout output current i ol ? ? ? 1 ma constant current output i out outn 1.5 ? 90 ma ac items (unless otherwise specified, v dd = 3.0 to 5.5 v, t a = ? 40c to 85c) characteristics symbol te s t circuits test conditions min typ. max unit serial data transfer frequency f sck 6 ? ? ? 25 mhz t hold1 6 ? 5 ? ? ns hold time t hold2 6 ? 5 ? ? ns t setup1 6 ? 5 ? ? ns setup time t setup2 6 ? 5 ? ? ns maximum clock rise time t r 6 *1 ? ? 500 ns maximum clock fall time t f 6 *1 ? ? 500 ns note1: if the device is connected in a cascade and the tr/tf of t he clock waveform increases due to deceleration of the clock waveform,it may not be possible to achieve the timing required for data transfer. pl ease keep these timing conditions in mind when designing your application.
tc62d749afg/afnag/bfnag 2011-02-10 7 electrical characteristics (unless otherwise specified, v dd = 3.3v, t a = 25c) characteristics symbol te s t circuits test conditions min typ. max unit high level logic output voltage v oh 1 i oh = ? 1 ma v dd ? 0.4 ? ? v low level logic output voltage v ol 1 i ol = + 1 ma ? ? 0.4 v high level logic input current i ih 2 v in = v dd , oe , sin, sck ? ? 1 a low level logic input current i il 3 v in = gnd, slat , sin, sck ? ? ? 1 a power supply current i dd 4 r ext = 1.2 k , all output on ? ? 8.0 ma output current i out 5 v dd = 3.3 v, v out = 1.0 v, r ext = 1.2 k , 1 output on ? 14.4 ? ma constant current error(ch to ch) s rank i out(ch) 5 v dd = 3.3 v, v out = 1.0 v, r ext = 1.2 k , 1 output on ? ? 1.5 % constant current error(ic to ic) s rank i out(ic) 5 v dd = 3.3 v, v out = 1.0 v, r ext = 1.2 k , 1 output on ? ? 1.5 % constant current error(ch to ch) n rank i out(ch) 5 v dd = 3.3 v, v out = 1.0 v, r ext = 1.2 k , 1 output on ? ? 2.5 % constant current error(ic to ic) n rank i out(ic) 5 v dd = 3.3 v, v out = 1.0 v, r ext = 1.2 k , 1 output on ? ? 2.5 % output off leak current i ok 5 v dd = 3.3 v, v out = 17 v, r ext = 1.2 k ? ? 0.5 a constant current power supply voltage regulation %v dd 5 v dd = 3.0 to 3.6 v, v out = 1.0 v, r ext = 1.2 k , 1 output on ? 1 5 %/v constant current output voltage regulation %v out 5 v dd = 3.3 v, v out = 1.0 to 3.0 v, r ext = 1.2 k , 1 output on ? 0. 1 0. 5%/v pull-up resistor r up 3 oe 400 500 600 k pull-down resistor r down 2 slat 240 300 360 k
tc62d749afg/afnag/bfnag 2011-02-10 8 electrical characteristics (unless otherwise specified, v dd = 5.0v, t a = 25c) characteristics symbol te s t circuits test conditions min typ. max unit high level logic output voltage v oh 1 i oh = ? 1 ma v dd ? 0.4 ? ? v low level logic output voltage v ol 1 i ol = + 1 ma ? ? 0.4 v high level logic input current i ih 2 v in = v dd , oe , sin, sck ? ? 1 a low level logic input current i il 3 v in = gnd, slat , sin, sck ? ? ? 1 a power supply current i dd 4 r ext = 1.2 k , all output on ? ? 8.0 ma output current i out 5 v dd = 5.0 v, v out = 1.0 v, r ext = 1.2 k , 1 output on ? 14.4 ? ma constant current error(ch to ch) s rank i out(ch) 5 v dd = 3.3 v, v out = 1.0 v, r ext = 1.2 k , 1 output on ? ? 1.5 % constant current error(ic to ic) s rank i out(ic) 5 v dd = 3.3 v, v out = 1.0 v, r ext = 1.2 k , 1 output on ? ? 1.5 % constant current error(ch to ch) n rank i out(ch) 5 v dd = 5.0 v, v out = 1.0 v, r ext = 1.2 k , 1 output on ? ? 2.5 % constant current error(ic to ic) n rank i out(ic) 5 v dd = 5.0 v, v out = 1.0 v, r ext = 1.2 k , 1 output on ? ? 2.5 % output off leak current i ok 5 v dd = 5.0 v, v out = 17 v, r ext = 1.2 k ? ? 0.5 a constant current power supply voltage regulation %v dd 5 v dd = 4.5 to 5.5 v, v out = 1.0 v, r ext = 1.2 k , 1 output on ? 1 5 %/v constant current output voltage regulation %v out 5 v dd = 5.0 v, v out = 1.0 to 3.0 v, r ext = 1.2 k , 1 output on ? 0. 1 0. 5%/v pull-up resistor r up 3 oe 400 500 600 k pull-down resistor r down 2 slat 240 300 360 k
tc62d749afg/afnag/bfnag 2011-02-10 9 switching characteristics (unless otherwise specified, v dd = 3.3v, t a = 25c) characteristics symbol te s t circuits test conditions min typ. max unit sck- out0 t plh1 6 slat = ?h?, oe = ?l? ? 30 40 ns slat - out0 t plh2 6 oe = ?l? ? 30 40 ns oe - out0 t plh3 6 slat = ?h? ? 30 40 ns sck-sout t plh 6 c l =10.5 pf 10 20 35 ns sck- out0 t phl1 6 slat = ?h?, oe = ?l? ? 30 40 ns slat - out0 t phl2 6 oe = ?l? ? 30 40 ns oe - out0 t phl3 6 slat = ?h? ? 30 40 ns propagation delay time sck-sout t phl 6 c l =10.5 pf 10 20 35 ns output rise time t or 6 10 to 90% of voltage waveform ? 10 20 ns output fall time t of 6 90 to 10% of voltage waveform ? 10 20 ns enable pulse width t woe 6 oe = ?h? or ?l? 25 ? ? ns clock pulse width t wsck 6 sck = ?h? or ?l? 20 ? ? ns latch pulse width t wslat 6 slat = ?h? 20 ? ? ns switching characteristics (unless otherwise specified, v dd = 5.0v, t a = 25c) characteristics symbol te s t circuits test conditions min typ. max unit sck- out0 t plh1 6 slat = ?h?, oe = ?l? ? 30 40 ns slat - out0 t plh2 6 oe = ?l? ? 30 40 ns oe - out0 t plh3 6 slat = ?h? ? 30 40 ns sck-sout t plh 6 c l =10.5 pf 10 20 35 ns sck- out0 t phl1 6 slat = ?h?, oe = ?l? ? 30 40 ns slat - out0 t phl2 6 oe = ?l? ? 30 40 ns oe - out0 t phl3 6 slat = ?h? ? 30 40 ns propagation delay time sck-sout t phl 6 c l =10.5 pf 10 20 35 ns output rise time t or 6 10 to 90% of voltage waveform ? 10 20 ns output fall time t of 6 90 to 10% of voltage waveform ? 10 20 ns enable pulse width t woe 6 oe = ?h? or ?l? 25 ? ? ns clock pulse width t wsck 6 sck = ?h? or ?l? 20 ? ? ns latch pulse width t wslat 6 slat = ?h? 20 ? ? ns
tc62d749afg/afnag/bfnag 2011-02-10 10 test circuits sck sin oe vdd out0 out7 out15 sout gnd rext i o = -1ma to 1ma c l = 10.5 pf v dd = 3.3 v, 5.0 v f. g v ih = v dd v il = 0 v t r = t f = 10 ns (10 to 90%) slat test circuit1: high level logic input voltage / low level logic input voltage r ext v sck sin oe vdd out0 out7 out15 sout gnd rext c l = 10.5 pf v dd = 3.3 v, 5.0 v slat test circuit2: high level logic input current / pull-down resistor r ext v in = v dd a a a a sck sin oe vdd out0 out7 out15 sout gnd rext c l = 10.5 pf v dd = 3.3 v, 5.0 v slat test circuit3: low level logic input current / pull-up resistor r ext a a a a
tc62d749afg/afnag/bfnag 2011-02-10 11 test circuit4: po wer supply current test circuit5: constant current output / output off leak curr ent / constant current error test circuit5: constant current power supply voltage regulati on / constant current output voltage regulation sck sin oe vdd out0 r l = 300 c l out7 c l r l out15 c l = 10.5 pf r l sout gnd rext c l = 10.5 pf v dd = 3.3 v, 5.0 v slat test circuit6: switching characteristics r ext = 1.2k f. g v ih = v dd v il = 0 v t r = t f = 10 ns (10 to 90%) v led = 5.32 v v out = 1.0~3.0 v, 17 v sck sin oe vdd out0 out7 out15 sout gnd rext c l = 10.5 pf v dd = 3.0~3.6 v, 4.5~5.5 v slat f. g v ih = v dd v il = 0 v t r = t f = 10 ns (10 to 90%) a a a r ext = 1.2k sck sin oe vdd out0 out7 out15 sout gnd rext c l = 10.5 pf v dd = 3.3 v, 5.0 v slat r ext = 1.2k f. g v ih = v dd v il = 0 v t r = t f = 10 ns (10 to 90%) a v out = 1.0 v
tc62d749afg/afnag/bfnag 2011-02-10 12 timing waveforms 1. sck, sin, sout 2. sck, sin, slat , oe , out0 3. oe , out0 ~ 15out 10% 90% 10% 90% t or out0 ~ 15out off on 50% 50% 50% 50% t woe tplh3 tphl3 oe t of t woe 50% t hold2 sin sck 50% 50% 50% 50% t phl1 /t plh1 t phl2 /t plh2 t wslat oe out0 50% slat 50% t setup2 t hold1 t plh /t phl t wsck 50% 50% 50% 50% t setup1 sin sck sout 50% 90% 10% t r t f 90% 10% t wsck 50%
tc62d749afg/afnag/bfnag 2011-02-10 13 power on reset (por) it avoids the malfunction by resetting all internal data of ic and setting default in startup. por circuit operates only when v dd rises from 0 v. to restart por, v dd should be 0.5 v or less. as for the voltage of storing the internal data, it is guaranteed after v dd reaches 3.0 v or more once. v dd waveform por workin g ran g e beyond por working range por working range v dd =2.8 v v dd =0.1 v v dd =0 v end of por v dd voltage for end of reset v dd =3.0v v dd voltage for guaranteed data
tc62d749afg/afnag/bfnag 2011-02-10 14 reference data *this data is provided for reference only. thorough evaluation and testing should be implemented when designing your application's mass production design. output current (i out ) ? output current setting resistance (r ext ) i out - r ext 0 10 20 30 40 50 60 70 80 90 0 1000 2000 3000 4000 5000 r ext ( ? ) i out (ma) theoretical formula i out (a) = (1.04(v) y r ext (: )) u 16.6 v out =1.0v t a =25c
tc62d749afg/afnag/bfnag 2011-02-10 15 reference data *this data is provided for reference only. thorough evaluation and testing should be implemented when designing your application's mass production design. output current (i out ) ? output voltage (v out ) i out - v out v dd =3.3v,ta=25 ,1chon 0 10 20 30 40 50 60 70 80 90 100 0 0.5 1 1.5 2 2.5 3 v out (v) i out (ma) i out - v out v dd =5.0v,ta=25 ,1chon 0 10 20 30 40 50 60 70 80 90 100 0 0.5 1 1.5 2 2.5 3 v out (v) i out (ma)
tc62d749afg/afnag/bfnag 2011-02-10 16 application circuit: general compos ition for static lighting of leds in the following diagram, it is reco mmended that the led supply voltage (v led ) be equal to or greater than the sum of v f (max) of all leds plus1.0v. ?` sin sck v led sout sout sin sck tc62d749afg/afnag/bfnag tc62d749afg/afnag/bfnag rext rext gnd gnd 1out 14out 15out 0out 1out 14out 15out 0out oe slat oe slat r ext r ext
tc62d749afg/afnag/bfnag 2011-02-10 17 application circuit: general compos ition for dynamic lighting of leds in the following diagram, it is reco mmended that the led supply voltage (v led ) be equal to or greater than the sum of v f (max) of all leds plus1.0v. example) td62m8600fg 8 bit mult ichip pnp transistor array. it is not necessary when lighting statically. ?` sin sck sout sin sck tc62d749afg/afnag/bfnag rext rext gnd gnd tc62d749afg/afnag/bfnag oe slat 0out oe slat 1out 14out 15out 0out 1out 14out 15out r ext r ext
tc62d749afg/afnag/bfnag 2011-02-10 18 notes on design of ics 1. power on sequence after power is on, data sett ing will be available in 10 s when v dd exceeds 3.0 v. please input serial data transfer frequency (sck), serial data(sin), latch( slat ) in 10 s when v dd exceeds 3.0 v. 2. regarding decoupling capacitor between power supply and gnd it is recommended that decoupling capacitor between power supply and gnd should place as near ic as possible. 3. regarding resistors for setting of output current when resistors for setting of output current (r ext ) are used commonly by many ics, in designing for mass production, take enough care in evaluating ic operation. 4. regarding pcb layout there is only one gnd terminal on this device when the inductance in the gnd line and the resistor are large, the device may malfunction due to the gnd noise when output swit ching by the circuit board pattern and wiring. therefore, take care when designi ng the circuit board pattern layout and the wiring from the controller. 5. please check the latest technical mate rial at the time of mass production. power on sequence
tc62d749afg/afnag/bfnag 2011-02-10 19 package dimensions weight: 0.29 g (typ.)
tc62d749afg/afnag/bfnag 2011-02-10 20 package dimensions ssop24-p-150-0.64 unit : inch weight: 0.14 g (typ.) 0.337 to 0.344 0.229 to 0.244 0.150 to 0.157 0.0325(ref) 0.025 0.008 to 0.012 0.004 to 0.098 0.054 to 0.068 0.016 to 0.034 0.010(typ)
tc62d749afg/afnag/bfnag 2011-02-10 21 notes on contents 1. block diagrams some of the functional blocks, circuits, or constants in the block diagram may be omitted or simplified for explanatory purposes. 2. equivalent circuits the equivalent circuit diagrams may be simplified or some parts of them may be omitted for explanatory purposes. 3. timing charts timing charts may be simplified for explanatory purposes. 4. application circuits the application circuits shown in this document are provided for reference purposes only. thorough evaluation is required, especially at the mass production design stage. toshiba does not grant any license to any industrial property rights by providing these examples of application circuits. 5. test circuits components in the test circuits are used only to ob tain and confirm the device characteristics. these components and circuits are not gua ranteed to prevent malfunction or failure from occurring in the application equipment.
tc62d749afg/afnag/bfnag 2011-02-10 22 ic usage considerations notes on handling of ics [1] the absolute maximum ratings of a semiconductor devic e are a set of ratings that must not be exceeded, even for a moment. do not exceed any of these ratings. exceeding the rating(s) may cause the device breakdown, damage or det erioration, and may result injury by explosion or combustion. [2] use an appropriate power supply fuse to ensure that a large current does not continuously flow in case of over current and/or ic failure. the ic will fully br eak down when used under conditions that exceed its absolute maximum ratings, when the wiring is routed im properly or when an abnormal pulse noise occurs from the wiring or load, causing a large current to continuously flow and the breakdown can lead smoke or ignition. to minimize the effects of the flow of a lar ge current in case of breakdown, appropriate settings, such as fuse capacity, fusing time and insertion circuit location, are required. [3] if your design includes an inductive load such as a motor coil, incorporate a protection circuit into the design to prevent device malfunction or breakdown caused by the current resulting from the inrush current at power on or the negative current resulting from the back electromotive force at power off. ic breakdown may cause injury, smoke or ignition. use a stable power supply with ics with built-in protec tion functions. if the power supply is unstable, the protection function may not operate, causing ic breakdown. ic breakdown may cause injury, smoke or ignition. [4] do not insert devices in the wrong orientation or incorrectly. make sure that the positive and negative termi nals of power supplies are connected properly. otherwise, the current or power consumption may exceed the absolute maximum rating, and exceeding the rating(s) may cause the device breakdown, dam age or deterioration, and may result injury by explosion or combustion. in addition, do not use any device that is applied the current with inserting in the wrong orientation or incorrectly even just one time. [5] carefully select external components (suc h as inputs and negative feedback capacitors) and load components (such as speakers), for example, power amp and regulator. if there is a large amount of leakage current such as input or negative feedback condenser, the ic output dc voltage will increase. if this output voltage is conne cted to a speaker with low input withstand voltage, overcurrent or ic failure can cause smoke or ignition. (the over current can cause smoke or ignition from the ic itself.) in particular, please pay attention when using a bridge tied load (btl) connection type ic that inputs output dc voltage to a speaker directly. points to remember on handling of ics (1) heat radiation design in using an ic with large current flow such as power amp, regulator or driver, please design the device so that heat is appropriately radiated, not to exceed the specified junction temperature (t j ) at any time and condition. these ics generate heat even during norm al use. an inadequate ic heat radiation design can lead to decrease in ic life, deterioration of ic char acteristics or ic breakdow n. in addition, please design the device taking into considerate the effect of ic heat radiation with peripheral components. (2) back-emf when a motor rotates in the reverse direction, stops or slows down abruptly, a current flow back to the motor?s power supply due to the effect of back-emf. if the current sink capability of the power supply is small, the device?s motor power supply and output pins might be exposed to conditions beyond maximum ratings. to avoid this problem, take the effect of back-emf into consideration in system design.
tc62d749afg/afnag/bfnag 2011-02-10 23 about solderability, following conditions were confirmed solderability (1) use of sn-37pb solder bath solder ba th temperature: 230 c dipping time: 5 seconds the number of times: once use of r-type flux (2) use of sn-3.0ag-0.5cu solder bath solder ba th temperature: 245 c dipping time: 5 seconds the number of times: once use of r-type flux
tc62d749afg/afnag/bfnag 2011-02-10 24 restrictions on product use ? toshiba corporation, and its subsidiaries and affiliates (collectively ?toshiba?), reserve the right to make changes to the in formation in this document, and related hardware, software a nd systems (collectively ?product?) without notice. ? this document and any information herein may not be reproduc ed without prior written permission from toshiba. even with toshiba?s written permission, reproduc tion is permissible only if reproducti on is without alteration/omission. ? though toshiba works continually to improve product?s quality a nd reliability, product can malfunction or fail. customers are responsible for complying with safety standards and for prov iding adequate designs and safeguards for their hardware, software and systems which minimize risk and avoid sit uations in which a malfunction or failure of product could cause loss of human life, b odily injury or damage to property, including data loss or corruption. before customers use the product, create designs including the product, or incorporate the product into their own app lications, customers must also refer to and comply with (a) the latest versions of all relevant toshiba information, including without limitation, this document, the specificati ons, the data sheets and application notes for product and the precautions and conditions set forth in the ?toshiba semiconductor reliability handbook? and (b) the instructio ns for the application with which the product will be used with or for. customers are solely responsible for all aspects of their own product design or applications, including but not lim ited to (a) determining the appropriateness of the use of this product in such des ign or applications; (b) evaluating and dete rmining the applicability of any information contained in this document, or in charts, dia grams, programs, algorithms, sample application circuits, or any other referenced document s; and (c) validating all operating paramete rs for such designs and applications. toshiba assumes no liability for customers? product design or applications. ? product is intended for use in general el ectronics applications (e.g., computers, personal equipment, office equipment, measur ing equipment, industrial robots and home electroni cs appliances) or for specif ic applications as expre ssly stated in this document. product is neither intended nor warranted for use in equipment or systems that require extraordinarily high levels of quality a nd/or reliability and/or a malfunction or failure of which may cause loss of human life, bodily injury, serious property damage or se rious public impact (?unintended use?). unintended use includes, without limitation, equipment used in nuclear facilities, equipment used in the aerospace industry, medical equipment, equi pment used for automobiles, trains, ships and other transportation, traffic signalin g equipment, equipment used to control combustions or explosions, safety dev ices, elevators and escalators, devices related to el ectric power, and equipment used in finance-related fi elds. do not use product for unintended us e unless specifically permitted in thi s document. ? do not disassemble, analyze, reverse-engineer, alter, modify, translate or copy product, whether in whole or in part. ? product shall not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable laws or regulations. ? the information contained herein is pres ented only as guidance for product use. no re sponsibility is assumed by toshiba for an y infringement of patents or any other intellectual property rights of third parties that may result from the use of product. no license to any intellectual property right is granted by this document, whether express or implied, by estoppel or otherwise. ? absent a written signed agreement, except as provid ed in the relevant terms and conditions of sale for product, and to the maximum extent allowable by law, toshiba (1) assumes no liability whatsoever, including without limitation, indirect, co nsequential, special, or incidental damages or loss, including without limitation, loss of profit s, loss of opportunities, business interruption and loss of data, and (2) disclaims any and all express or implied warranties and conditions related to sale, use of product, or information, including warranties or conditions of merchantability, fitness for a particular purpose, accuracy of information, or noninfringement. ? do not use or otherwise make available product or related software or technology for any military purposes, including without limitation, for the design, development, use, stockpil ing or manufacturing of nucl ear, chemical, or biological weapons or missile technolog y products (mass destruction weapons). product and related softwa re and technology may be contro lled under the japanese foreign exchange and foreign trade law and the u.s. export administration r egulations. export and re-export of product or related softw are or technology are strictly prohibit ed except in compliance with all app licable export laws and regulations. ? please contact your toshiba sales representative for details as to environmental matters such as the rohs compatibility of pro duct. please use product in compliance with all applicable laws and regula tions that regulate the inclus ion or use of controlled subs tances, including without limitation, the eu rohs directive. toshiba assumes no liability for damages or losses occurring as a result of noncompliance with applicable laws and regulations.

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